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AK4113
S/PDIF 接受器，192kHz，6 输入
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- AES/EBU, IEC60958, S/PDIF, EIAJ CP1201 Compatible
- Low Jitter Analog PLL
- PLL Lock Range: 8k ~ 216kHz
- Clock source: PLL or X'tal
- 6-channel Receiver Input and 1-channel Transmission Output (Through output)
- Auxiliary Digital Input
- De-emphasis for 32kHz, 44.1kHz and 48kHz
- Detection Functions
- Non-PCM Bit Stream Detection
- DTS-CD Bit Stream Detection
- Sampling Frequency Detection
(8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz)
- Unlock & Parity Error Detection
- Validity Detection
- DAT Start ID Detection
- Up to 24bit Audio Data Format
- Audio I/F: Master or Slave Mode
- 40-bit Channel Status Buffer
- Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
- Q-subcode Buffer for CD bit stream
- Serial ??P I/F: I2C (max. 400kHz) or 4-wire
- Two Master Clock Outputs: 64fs/128fs/256fs/512fs
- Operating Voltage: 2.7 to 3.6V with 5V tolerance
- Small Package: 30pin VSOP
- Ta: 40 - 85°C
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AK4113 BLOCK DIAGRAM
Data Sheet PDF
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Data Sheets
Rev. MS0078-E-02 2004/04
PDF : 335KB / 30pages
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Evalution Board Manual
Rev. KM080200 2005/10
PDF : 415KB / 25pages |
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